Metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors are among the most widely used capacitors in integrated circuits. FIG. 1 illustrates a typical MIM capacitor, which includes bottom plate 2, top plate 6, and insulation layer 4 therebetween. The bottom plate 2 and top plate 6 are formed of conductive materials.
As is known in the art, the capacitance of a capacitor is proportional to its area and the dielectric constant (k) of the insulation layer, and is inversely proportional to the thickness of the insulation layer. Therefore, to increase the capacitance, it is preferable to increase the area and the k value and to reduce the thickness of the insulation layer. However, the thickness and the k value are often limited by the technology used for forming the capacitor. For example, the thickness cannot be less than what the existing technology allows. On the other hand, since the capacitors are often formed in low-k dielectric layers, the ability to increase the k value is also limited.
Methods for increasing the area of the capacitor have been explored. A problem associated with increasing area is that greater chip area is required. This dilemma is solved by the introduction of vertical (multi-layer) capacitors. A typical vertical MOM capacitor 10 is shown in FIGS. 2, 3, and 4. FIG. 2 illustrates a perspective view of MOM capacitor 10, which includes metal electrodes 12 and 14 separated by dielectric materials. Each of the metal electrodes 12 and 14 forms a three-dimensional structure. For clarity, metal electrode 12 is not shaded, while metal electrode 14 is shaded with dots.
Each of the metal electrodes 12 and 14 includes more than one layer interconnected by vias. FIG. 3 illustrates a top view of a first metal layer (please refer to the middle layer in FIG. 2). Metal electrode 12 includes fingers 122, and bus 121 for interconnecting fingers 122. Metal electrode 14 includes fingers 142, and bus 141 for interconnecting fingers 142. Fingers 122 and 142 are placed in an alternating pattern with a very small space between the neighboring fingers. Therefore, each finger 122/142 forms a sub capacitor(s) with its neighboring fingers 142/122 or a bus 141/121. The total capacitance is equivalent to the sum of the sub capacitors.
FIG. 4 illustrates a top view of the capacitor 10 in a second metallization layer (refer to the top or the bottom layer in FIG. 2), which overlies the bottom metallization layer. Typically, the direction of the fingers in the second metallization layer is orthogonal to the direction of the fingers in the bottom metallization layer. Similarly, electrodes 12 and 14 in the second metallization layer include buses 121 and 141 and a plurality of fingers 122 and 142, respectively. Typically, buses 121 in all the layers have similar shapes and sizes and are overlapped vertically. Buses 141 in all the layers also have similar shapes and sizes and are overlapped vertically. Vias 16 connect buses 121 in the first and the second metallization layers, thereby forming an integral electrode 12. Similarly, vias 18 connect buses 141 in neighboring layers, thereby forming an integral electrode 14.
To further increase the capacitance of MOM capacitors, the regions underlying the bottom metallization layer were also used to form a layer of the MOM capacitors. The resulting structure is similar to the structure as shown in FIG. 2, except that layer 1 of the MOM capacitor 10 is now formed in an inter-layer dielectric layer. Referring back to FIG. 3, in this case, electrodes 12 and 14 are formed of doped polysilicon, and layers 1 and 2 are interconnected by contact plugs, instead of vias.
The introduction of the polysilicon MOM layer results in the increase in capacitance of the MOM capacitors. However, the use of polysilicon causes the degradation of the high-frequency response of the MOM capacitors, particularly at frequencies of about 1 GHz or higher. For example, the Q-factors of the capacitors having polysilicon layers may be degraded by about 74% compared to the MOM capacitors that have all layers formed of metals. Accordingly, new structures and manufacturing methods are needed to take advantage of the increased capacitance by forming a capacitor layer underlying the bottom metallization layer, without sacrificing high-frequency response.